Aubrac core
Aubrac is a french breed of cows from the Plateau de l’Aubrac in the south-central of France. It is mainly raised for its meat, but also for its milk which can be used for the Laguiole cheese.
This page and the following ones describe the Aubrac core. It is single issue in-order CPU build around a classic pipeline and two levels of cache memories. Based on the RISC-V ISA, it is developed in Chisel3 and has a lot of different parameters (the data size, the number of stages, the supported extensions etc).
Overview
The Figure 1 represents the whole Aubrac core.
It is composed of 8 parts.
The Front-End is responsible for the instruction fetch.
The NLP is used to predict control-flow changes.
The Back-End is responsible for the decoding and the execution of the instructions.
The Hardware Field Unit (HFU) is an execution unit dedicated to fields management (CHAMP ISA).
The I/O module is used for core’s specific memory addressable mechanism (e.g. privileged timers).
L1I, L1D and L2 are respectively the Level 1 Instruction, Level 1 Data and the Level 2 (Instruction and Data) private cache memories.
ISA support
The Aubrac core is based on the RISC-V ISA. It currently supports both 32 and 64 bits bases.
Extension | Version | Implemented ? | Tested ? | Optional ? | Dependencies |
---|---|---|---|---|---|
M | 2.0 | ||||
A | 2.1 | ||||
B | 1.0.0 | ||||
Zicsr | |||||
Zicntr | |||||
Zifencei | 2.0 |
As described on the Table 1, multiple extensions are currently implemented in the Aubrac. Most of them are optional: the dedicated hardware parts are completely removed during Verilog generation.
If both 32 and 64 bits are implemented, only 32 bits version is currently used and tested. More work is needed to verify 64 bit specific instructions, like ones dedicated to word-size datas.