Biography

I am post-doctoral researcher in computer security at the LAAS-CNRS of Toulouse in France. I work with Vincent Migliore on the design of processors secure against side-channel attacks (power consumption and electromagnetic fields measurements).
Previously, I was graduated from the PHELMA - Grenoble INP engineering school in electronics and microelectronics. Then, during my PhD, I was working at Inria in the CIDRE Team advised by Ronan Lashermes.
Elephant at sunset
Mathieu Escouteloup

Interests

  • Processor architecture
  • Digital design
  • Hardware security
  • Hardware/Software interface
  • Side-channel attacks

Professionnal experience

  • 2021/11 - Now: Post-doctoral researcher
    LAAS-CNRS, Toulouse, France
  • 2018/10 - 2021/09: PhD student
    Inria, Rennes, France
  • 2015/09 - 2018/08: Apprentice engineer
    Dolphin Integration (now Dolphin Design), Meylan, France

Education

Teaching

During both my PHD and post-doctoral contract, I was teachning assistant for the following courses:
Course Institution Year Level
Digital design - VHDL Université de Rennes 1 2019-2021 Master 1
Assembly language - Arm INSA Toulouse 2021-2023 Licence 3
Object-Oriented Programming - C++ INSA Toulouse 2021-2022 Licence 3
Computer architecture INSA Toulouse 2022-2023 Licence 2
Microcontrollers - C INSA Toulouse 2022-2023 Master 1

Publications

2021

  • Ensuring microarchitectural isolation in processors.
    Mathieu Escouteloup
    PhD Thesis
    Theses.fr Slides

  • Under the dome: preventing hardware timing leakages
    Mathieu Escouteloup, Ronan Lashermes, Jacques Fournier et Jean-Louis Lanet
    International Conference on Smart Card Research and Advanced Applications (CARDIS 2021)
    HAL Conference Slides

  • Electromagnetic Fault Injection against a Complex CPU, toward New Micro-Architectural
    Fault Models
    Thomas Trouchkine, Sébanjila Kevin Bukasa, Mathieu Escouteloup, Ronan Lashermes et Guillaume Bouffard
    Journal of Cryptographic Engineering (JCEN 2021)
    HAL

2020

  • Recommendations for a Radically Secure ISA
    Mathieu Escouteloup, Jacques Fournier, Jean-Louis Lanet and Ronan Lashermes
    Fourth Workshop on Computer Architecture Research with RISC-V (CARRV 2020)
    HAL Workshop Slides

Talks

2021

  • Preventing timing information leakages from the microarchitecture
    Mathieu Escouteloup, Ronan Lashermes, Christophe Bidan and Jacques FournierS
    2nd RISC-V Week
    Workshop Slides

2019

  • Microarchitecture security
    Mathieu Escouteloup, Ronan Lashermes, Jean-Louis Lanet and Jacques Fournier
    Workshop on Practical Hardware Innovation in Security and Characterization (PHISIC 2019)
    Workshop Slides

Projects

  • IDROMEL - Improving the Design of secure systems by a Reduction Of Micro-
    architectural Effects on side-channeL attacks
    ANR